Chemical-Mechanical Planarization, also referred to as Chemical-Mechanical Polishing or simply CMP, is commonly used in the manufacture of semiconductor devices and denotes the process of removing material and forming a substantially planar surface before additional layers are deposited and/or additional patterning of the layers occurs. An accepted method of polishing semiconductor devices involves polishing a surface of the semiconductor with a polishing composition and a polishing pad. In a typical CMP process, a semiconductor wafer is pressed against the polishing pad in the presence of the polishing composition under controlled chemical, pressure, velocity, and temperature conditions. The polishing composition generally contains small, abrasive particles that abrade the surface of the wafer in a mixture with chemicals that oxidize and/or otherwise act upon the newly formed surface of the wafer. A polishing composition that contains abrasives is typically known as a slurry, while a composition that is free from abrasives can be simply termed a solution.
CMP processes have been extensively studied for use in semiconductor fabrication and constitute integral steps in many practical production environments. CMP of metal-containing layers has been studied most extensively in connection with metals such as tungsten, copper, aluminum, tantalum, among others, as well as oxides, nitrides, and alloys thereof. See, e.g., Chemical Mechanical Planarization of Microelectronic Materials, by J. M. Steigerwald, S. P. Murarka and R. J. Gutmann (John Wiley & Sons 1997), especially Chapters 5-8. Metals, including tungsten, often compose certain features of a layer in semiconductor fabrication, while other features are composed of a dielectric material.
The polishing of the semiconductor substrate, usually one or more metals over a layer of a dielectric material, uses a CMP slurry comprising abrasives (which may be in the slurry or in the pad), an oxidizer, and one or more additives such as chelators, accelerators, pasivators, and the like. Historically, manufacturers have used formulations that provide very high selectivity between the metal layer and the dielectric material, and formulations that provide very high removal rates. Selectivity is the difference in the rate at which metal is removed compared to the rate at which the dielectric is removed. By high specificity the manufacturers usually require the CMP formulation to, under typical polishing conditions, remove at metal at a rate at least twice as fast, usually at least ten times as fast or more, as the CMP formulation removes the dielectric. Indeed, while selectivity has always been a goal of manufacturers, it is central to U.S. Pat. No. 6,062,952 which claims a process of planarizing a material selected from a group consisting of a dielectric, silicon dioxide, tungsten, polysilicon, aluminum, copper, and Si3N4; the process comprising polishing a first material at a removal rate equal to X, and continuing polish until there is a second material having a removal rate of not greater than X/4. For tungsten, selectivities are much higher—U.S. Pat. No. 5,916,855 provides an improved slurry having tungsten removal rates near 5000 angstroms per minute and greater selectivity than can be obtained with slurries in the prior art, where “the prior art teaches that tungsten to TEOS polish rate selectivity for CMP is less than 180 . . . (and) that high tungsten/TEOS selectivity requires reduced tungsten polish removal rate.” By high rate, the manufacturers usually specify metal removal rates in the range of 3500 to 6000 angstroms of tungsten per minute.
Generally, CMP is performed with a slurry and a pad, where slurry disposed between the downward forcing pad and the substrate aggressively abrades the substrate. The oxidizers react with exposed metal to form metal oxides, which are more readily abraded by the abrasives. Since the pad is presumed to be planar, only the highest portions of the substrate should be polished, until eventually the entire substrate is planarized. A problem with prior art formulations is dishing, a phenomena where depressions are formed in the metal layer that extend below the plane of the surface of the polished substrate. Without being bound by theory, dishing may in part result because the surface to be polished has a topography that includes troughs, and during polishing the polishing slurry enters the troughs in a downward direction, and the abrasive particles contained in the slurry abrade the material in the bottom of the trough, albeit in a lesser amount than the higher points of the topography are abraded, and because the pad is resilient very small, gradual changes in topography will have material be removed rather evenly as opposed to planarizing out this slight defect. Dishing may also be caused or exacerbated by the very aggressive oxidizer chemistries used in modern CMP formulations.
Generally, the art when addressing dishing is concerned with copper substrates, because copper interconnects are typically made using the damascene process. The metal structures in such a copper wafer typically have a larger width than structures made with more conventional metals such as aluminum or tungsten. The damascene structure is a metal-filled trench in existing dielectric layers, and after filling the trench the excess metal is polished off before another dielectric layer is applied. As this is the final step, to prevent shorts caused by residual metal, the surface is generally over-polished to ensure that the only remaining metal is disposed within the trench. However, most metals experience dishing problems, including tungsten, especially if used in a damascene process.
Generally, the art addresses dishing by adding one or more film-forming agents, e.g., benzotriazole or polymeric agents, to the slurry to try to coat and thereby protect the troughs from the aggressive chemistries and from the impinging momentum of the slurry entering troughs in a downward direction. These film-formers, if not removed, can interfere with subsequent processing. Also, some modern low-k dielectrics are damaged by film formers. To ameliorate dishing, some manufacturers apply an excessive amount of tungsten, and thereby incur an increase in polishing time and expense. Other manufacturer are trying to planarize the surface either before polishing by filling inn troughs, or very early in the polishing process by not using oxidizers, to eliminate troughs. Yet other manufacturers are reducing dishing by placing a sacrificial dielectric layer disposed above a first dielectric, where the sacrificial dielectric layer is eventually removed by polishing, as described in U.S. Pat. No. 5,928,959.
CMP of tungsten over dielectric semiconductor surfaces encounters dishing problems. It is the object of the present invention to reduce dishing of tungsten features over a dielectric.